1.) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a transistor gate dielectric with a combination of high dielectric constant and low dielectric constant regions.
2.) Description of the Prior Art
In MOS (metal on silicon) transistor technology, a gate dielectric is formed on a silicon substrate, and a gate electrode is formed over the gate dielectric. Source and drain regions are formed adjacent the gate electrode and the gate dielectric. When a voltage is applied to the gate electrode, electrons (NMOS) or holes (PMOS) flow across the region of the silicon substrate under the gate dielectric, known as the channel. As the channel length decreases, the electrons in an NMOS transistor gain sufficient energy from the electric field to enter the gate dielectric layer where they become trapped, changing the gate threshold voltage (e.g. hot carrier effect).
To reduce the hot carrier effect, a lightly doped drain region LDD is formed between the channel and the source/drain, lowering the electric field. However, the reduced impurity concentration in the LDD causes parasitic resistance, reducing drive current and slowing down the transistor.
Another problem with LDD structured MOS transistors is that the overlap of the gate electrode over the LDD regions with a thin gate dielectric between them causes capacitance, called overlap capacitance, which further slows the transistor. The higher the dielectric constant, the greater the overlap capacitance.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,952,700 (Yoon) shows a process for forming a two-layer gate dielectric on one side of the gate.
U.S. Pat. No. 5,882,971 (Wen) shows a method for forming a read-only memory (ROM) using spacers (43) on the sidewall of s gate trench.
U.S. Pat. No. 5,736,435 (Venkatesan et al.) shows a gate in a trench with spacers on the trench.
It is an object of the present invention to provide a method for forming a gate dielectric having regions of varying dielectric constant.
It is another object of the present invention to provide a method for increasing drive current in a gate channel while reducing hot carrier effects and overlap capacitance.
It is yet another object of the present invention to provide a method for reducing channel length without causing detrimental short channel effects and overlap capacitance.
To accomplish the above objectives, the present invention provides a method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Sidewall spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the sidewall spacers. The sidewall spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.
The present invention provides considerable improvement over the prior art. A gate dielectric can be formed having regions with different dielectric constants. The high-K dielectric region allows the drive current (Idsat) in a gate channel to be increased. The low-K dielectric regions at the edges of the gate electrode reduce hot carrier effects and overlap capacitance. The gate dielectric of the present invention provides a method for reducing channel length without causing detrimental short channel effects and overlap capacitance.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.